(1) Field of Invention
The present invention relates to a power consumption reducing apparatus for a computer bus system and an associated method for reducing power consumption. Particularly, the present invention relates to reducing power consumption during a CPU idle condition when a bus master other than the CPU, such as a Direct Memory Access (DMA) controller or a refresh controller, uses the bus system. Power consumption is reduced by lowering or stopping a clock signal supplied to the CPU.
(2) Description of Related Art
Recently, development of computer technology has taken into consideration functional aspects as well as power saving aspects. Therefore, a Power Management System (PMS) is used in a personal computer to maximize power savings in accordance with a current operational state of the computer.
As illustrated in FIG. 1, the Power Management System (PMS) is divided into a normal mode 10, a doze mode 12, a standby mode 14, a suspend mode 16, and an off mode 18 in accordance with the power supply.
The normal mode 10 refers to the normal operational state of the system.
The doze mode 12 reduces the clock speed of the CPU 1/2, 1/4, or 1/8 when the system is inactive, e.g., when a hard disk is not accessed via the serial input/output interface, or when the video display, the FDD, the keyboard, etc., are not active.
The standby mode 14 reduces the clock speed of the CPU when there is no system activity, shuts off the video display, and/or places the HDD in a standby mode.
The suspend mode 16 stops or shuts off the CPU clock, the HDD, the FDD, and the video display, but not the memory, in order to reduce power usage.
The PMS restores the system to its normal mode 10 from the doze and standby modes 12, 14 if system activity is sensed. The system is restored from the suspend mode 16 by, for example, pushing a suspend/resume button on the computer. The system is switched between the normal mode 10 and the off mode 18 by a conventional on/off switch.
In conventional PMS processes, however, the CPU is supplied with a full speed clock signal when the FDD is accessed, or when a bus master (for example, a DMA controller, a refresh controller, a Small Computer System Interface (SCSI), an Enhanced Small Device Interface HDD controller, a LAN card, a sound card, etc.) is allowed to use the bus system.
Therefore, power consumption associated with the clock signal supplied to the CPU is increased when a bus master, other than the CPU, uses the bus, because the CPU performs only an internal calculation.